Embodiments of the present invention relate to digital circuits, and more particularly, to high speed memory circuits.
Caches and register files are high speed memory used to store instructions and operands for instructions. They are critical components of microprocessors because of requirements for high speed and reliability. A portion of a computer system with high speed memory is abstracted at a high level in FIG. 1. Microprocessor 102 comprises cache 104 and register files 106. Cache 104 may be part of a memory hierarchy to store instructions and data, where system memory 108 is part of the memory hierarchy. Communication between microprocessor 102 with memory 108 is facilitated by memory controller (or chipset) 110, which also facilitates in communicating with peripheral components 112. Microprocessor communicates directly with memory controller 110 via bus or point-to-point interconnect 114.
Because of the performance requirements placed upon caches and register files, high-performance domino type logic is often used. LOW-VT (low threshold voltage) transistors have been used in domino logic to improve speed, but the use of such devices may lead to an increase in sub-threshold leakage current. Sub-threshold leakage current may impact the performance of high speed memory if it is not reduced or taken into account.
Consider a typical implementation of a register file as illustrated in FIG. 2. For simplicity, FIG. 2 does not show any write ports, and shows only one read port (one local bit line). The bit line portion of a memory read port may be viewed as essentially a wide OR domino gate. In the particular example of FIG. 2, there are sixteen memory cells sharing local bit line 202, but for simplicity only memory cells 204 and 206 are shown, where word line 208 is used to access memory cell 204 during a read operation, and word line 210 is used to access memory cell 206 during a read operation. The clock signal is denoted by xcfx86. The clock signal xcfx86 is LOW (VSS) during a pre-charge phase, so that pMOSFET 212 is switched ON to pre-charge local bit line 202 HIGH (VCC). During an evaluation phase (read operation), the clock signal xcfx86 is HIGH so that pMOSFET 212 is OFF, and a half keeper comprising pMOSFET 214 and inverter 216 continues to keep local bit line 202 charged unless it is otherwise discharged by one or more of the memory cells sharing local bit line 202.
Ideally, local bit line 202 would only be discharged during a read operation if the information bit stored in the memory cell being read is such as to switch ON its associated access transistor. For example, if the state (stored information bit) of memory cell 204 is such that the gate voltage on access nMOSFET 218 is HIGH, then when word line 208 is HIGH during a read operation, memory cell 204 will discharge local bit line 202. If, on the other hand, the information bit stored in memory cell 204 is such that the gate of access nMOSFET 218 is LOW, then local bit line 202 should maintain its charged state so that the stored information bit is correctly read. However, in a worst-case scenario, all other memory cells not being read may be such that the gate voltages on their respective access nMOSFETs are all HIGH, and consequently the accumulative effect of sub-threshold leakage current through their respective access nMOSFETs may be sufficiently large to discharge local bit line 202 to a voltage in which an incorrect read result is performed. The half-keeper comprising pMOSFET 214 may be sized larger to contend with the sub-threshold leakage, but this leads to an increase energy dissipation as well as a decrease in performance.
Many techniques have been suggested and taught for mitigating the effects of sub-threshold leakage current in high speed memory, as discussed above. For example, the circuit of FIG. 3 is taught in xe2x80x9cA 0.13 um 6 GHz 256xc3x9732b Leakage-Tolerant Register File,xe2x80x9d by R. Krishnamurthy et al., 2001 Symposium on VLSI Circuits Digest of Technical Papers, pp. 25-26, 2001. For simplicity, FIG. 3 shows only two memory cells connected to local bit line 302, but in practice there may be many such memory cells. Referring to memory cell 304, when a read operation is performed on-this memory cell, word line 306 is held HIGH so that the source of access transistor 308 is brought to VSS, and the operation is similar to that of FIG. 2. However, when no read operation is being performed on memory cell 304, word line 306 is LOW, in which case pullup pMOSFET 310 charges the source of access transistor 308 to VCC. In this case, if local bit line 302 is HIGH, then both the source and drain of access transistor 308 are HIGH but its gate is at VSS, so that VDS is zero and VGS is xe2x88x92VCC, and consequently sub-threshold leakage current is essentially eliminated. (If local bit line 302 were LOW, then it was brought LOW by a memory cell being read, in which case sub-threshold leakage current is not an issue.)
However, if memory cell 304 is being read, and the stored information bit is such that the gate voltage of access transistor 308 is at VSS, then the gate-to-source voltage VGS=0 and the source-to-drain voltage VDS=VCC, and the resulting sub-threshold leakage current conducted by access transistor 308 should be supplied by the half-keeper to prevent false evaluation. Consequently, although unwanted sub-threshold leakage current for memory based upon the circuit of FIG. 3 is essentially eliminated when a word line is held LOW, there nevertheless may be unwanted sub-threshold leakage current during a read operation.